Field of the Invention
The present invention relates to a data processor having a plurality of registers, particularly to a data processor which is provided with an interrupt controller for controlling a plurality of interrupt factors with vectors, and operates simultaneously register contents specified by an address and a vector.
Description of Related Art
In a conventional data processor, being provided with an interrupt controller which manages a plurality of interrupt factors by vectors as well as has a control register for each factor, a daisy chain method for clearing an interrupt request flag of the interrupt factor after an interrupt request is received in an acknowledge cycle and a corresponding interrupt vector is read out is well known.
FIG. 1 is a block diagram of a conventional interrupt controller adopting such the method. In FIG. 1, a part of an internal block of an interrupt controller having k number of interrupt factors is shown.
In FIG. 1 reference numeral 1 designates an interrupt factor processing unit, and k number of interrupt factor processing units designated by reference characters 1-1 to 1-k corresponding to k number of interrupt factors are provided.
To each interrupt factor processing unit 1, a unique interrupt vector is allocated, and a control register 5 and an interrupt request latch 6 for latching an interrupt request are provided. In addition, corresponding to the respective interrupt factor processing units 1-1 to 1-k, the respective control registers are designated by reference characters 5-1 to 5-k, and the respective interrupt request latches by 6-1 to 6-k.
Further, to the respective interrupt factor processing units 1 except the lowest interrupt factor processing unit 1-k, respective interrupt request clear circuits 12 are provided. Corresponding to the respective interrupt factor processing units 1-1 to 1-k-1, the respective interrupt request clear circuit 12 are designated by the reference characters 12-1 to 12-k-1.
Reference numeral 13 designates a data bus, which can input or output data between a bus master 100, for example, CPU or the like, and the respective control registers 5-1 to 5-k and an interrupt vector register 8 to be described later.
Numeral 3 designates a master address decoder, which generates address decode signal 4 designating the control register 5 of one or other interrupt factor processing unit by decoding a master address 2 outputted from the bus master 100.
Numeral 9 designates a bus cycle effective signal outputted from the bus master 100. When the signal 9 becomes in assertion state, inputting or outputting data between the control register 5 of the interrupt factor processing unit 1 specified by the address decode signal 4 and the data bus 13 is possible.
Accordingly, a read/write operation to each control register 5 by the bus master 100 is performed as follows.
By that the master address 2 outputted from the bus master 100 is decoded by the master address decoder 3, the address decode signal 4 which specifies one or other interrupt factor processing unit 1 is generated. When the bus cycle effective signal 9 is in assertion state, the read/ write operation of data is performed between the control register 5 of the interrupt factor processing unit 1 specified by the address decode signal 4 and the bus master 100 through the data bus 13.
When an interrupt request is given from outside through a signal line (not shown), the interrupt request is latched to an interrupt request latch 6 of one or other interrupt Factor processing unit 1 corresponding to the inputted interrupt request. This state is called an interrupt request state.
Numeral 7 designates an interrupt priority control circuit, which judges whether or not the interrupt request is latched to the interrupt request latch 6 of each interrupt Factor processing unit 1. When the interrupt request is latched to one or other interrupt request latch 6, the interrupt priority control circuit 7 transfers an interrupt vector allocated to the interrupt factor processing unit 1 to the interrupt vector register 8 so as to latch the interrupt request. When the interrupt requests are latched to a plurality of interrupt request latches 6, the interrupt priority control circuit 7 transfers the interrupt vector allocated in the interrupt factor processing unit 1 having the highest priority among them to the interrupt vector register 8 so as to latch the interrupt vector.
Numeral 10 designates an interrupt vector register select signal, which is outputted from the bus master 100 when the bus master 100 selects the interrupt vector register 8 to read the interrupt vector latched by the interrupt vector register 8 so as to perform interrupt processing. In other words, when the interrupt processing is performed in such a way, it is necessary to clear the interrupt request which is the cause of the interrupt processing.
The interrupt vector register select signal 10 and the aforementioned bus cycle effective signal 9 are given to an AND gate 110 of 2 inputs. The output signal of the AND gate 110 is given to the interrupt request clear circuit 12 of the highest interrupt factor processing unit 1-1 as an interrupt vector register read signal 11. The interrupt request clear circuits 12-2 to 2-k-1 of the respective interrupt factor processing units 1 after the highest unit 1 are connected in daisy chain in order.
Thus, in the case where the bus cycle effective signal 9 is in assertion state, when the bus master 100 makes the interrupt vector select signal 10 be in assertion state in order to perform processing for the interrupt request, since the interrupt vector from the interrupt vector register 8 can be read out through the data bus 13, the bus master 100 performs the interrupt processing in accordance with the interrupt vector. At the same time, an interrupt vector register read signal 11 which is an output signal from the AND gate 110 becomes also in assertion state and is given to the interrupt request clear circuit 12-1 of the highest interrupt factor processing unit 1-1.
In the respective interrupt request clear circuits 12-1 to 12-k-1, the interrupt request clear circuit 12 of the interrupt factor processing unit 1 whose interrupt request is not received transmits to the interrupt request latch 6 of the interrupt factor processing unit 1 in the next stage that the interrupt vector register read signal 11 is effective. On the other hand, the interrupt request clear circuit 12 of the interrupt factor processing unit 1 whose interrupt request is received makes the interrupt vector register read signal 11 become ineffective as well as clears the request latch 6 of the interrupt factor processing unit in which the circuit 12 itself is included.
By that the respective interrupt request circuits 12 are operated in the way aforementioned, the interrupt vector register read signal 11 of in assertion state transmits through the respective interrupt request clear circuits 12 until the interrupt factor processing unit 1 whose interrupt request is received.
In the lowest, in other words, in the interrupt factor processing unit 1-k of the last stage, the interrupt request clear circuit 12 is not provided. But since the fact that the interrupt vector register read signal 11 of in the assertion state is transmitted until the interrupt factor processing unit 1-k means the case where the interrupt request of the interrupt factor processing unit 1-k of the last stage is received, therefore the interrupt request latch 6-k of the interrupt factor processing unit 1-k is necessarily cleared.
Since the interrupt controller of the conventional data processor is so configured as aforementioned, the delay time of the interrupt vector register read signal until the most end of the chain of the interrupt request clear circuit is the time of sum of the delay quantity of each interrupt factor processing unit. Therefore, when the number of the interrupt factor processing units is increased, the delay time of the interrupt vector register read signal until the most end of the chain of the interrupt request clear circuit becomes very long. Accordingly, in order to process a plurality of interrupt factors at high speed, such a method that the delay time of the interrupt vector register read signal does not depend upon the number of interrupt factors is required.